Add support for Qualcomm MBG driver and ADC5 Gen3 channels#664
Add support for Qualcomm MBG driver and ADC5 Gen3 channels#664raryan-qcom wants to merge 10 commits into
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
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Merge Check Failed: No Change Task Found No associated change tasks found for CR 4561965 on any of the following entities: Entities:
CR: 4561965 Please ensure the CR has a change task associated with at least one of the entities for this branch. |
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Merge Check Failed: CR Not Eligible for Merge CR 4561980 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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No checkpatch error were found. I ran the checkpatch on MakeFile also but it already had 74 warning even though we added one change. One mutex structure is added without comments, so checker is failing, requestion override now, in next time we will fix that. Please find below results of checkpatch for reference- (venv) raryan@hu-raryan-hyd:/local/mnt/workspace/raryan/qli2.0/kernel$ ./checkpatch.pl --no-tree -g 12a244b No typos will be found - file '/local/mnt/workspace/raryan/qli2.0/kernel/spelling.txt': No such file or directory WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? total: 0 errors, 2 warnings, 82 lines checked NOTE: For some of the reported defects, checkpatch may be able to Commit 12a244b ("FROMLIST: dt-bindings: thermal: Add Qualcomm MBG thermal monitor support") has style problems, please review. NOTE: If any of the errors are false positives, please report total: 0 errors, 1 warnings, 277 lines checked NOTE: For some of the reported defects, checkpatch may be able to Commit 6a1751c ("FROMLIST: thermal: qcom: Add support for Qualcomm MBG thermal monitoring") has style problems, please review. NOTE: If any of the errors are false positives, please report |
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Merge Check Failed: CR Not Eligible for Merge CR 4561980 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Merge Check Failed: No Change Task Found No associated change tasks found for CR 3828090 on any of the following entities: Entities:
CR: 3828090 Please ensure the CR has a change task associated with at least one of the entities for this branch. |
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Merge Check Failed: CR Not Eligible for Merge CR 3828090 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Merge Check Failed: CR Not Eligible for Merge CR 3828090 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Merge Check Failed: CR Not Eligible for Merge CR 3828090 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Merge Check Failed: CR Not Eligible for Merge CR 3828090 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Merge Check Failed: CR Not Eligible for Merge CR 3828090 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Merge Check Failed: CR Not Eligible for Merge CR 3828090 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Merge Check Failed: CR Not Eligible for Merge CR 3828090 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Merge Check Failed: CR Not Eligible for Merge CR 3828090 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
PR #664 — validate-patchPR: #664
Final Summary
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PR #664 — checker-log-analyzerPR: #664
Detailed report: Full report
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Add bindings for the Qualcomm MBG (Master Bandgap) temperature alarm peripheral found on the PM8775 PMIC. Unlike the existing SPMI temp alarm peripheral,the MBG peripheral supports both hot and cold threshold monitoring across two programmable levels (LVL1 and LVL2), with interrupt status reported via a fault status register over SPMI. Link: https://lore.kernel.org/all/20260601-spmi-mbg-driver-v1-1-b4892b55a17f@oss.qualcomm.com/ Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Co-developed-by: Sachin Gupta <sachin.gupta@oss.qualcomm.com> Signed-off-by: Sachin Gupta <sachin.gupta@oss.qualcomm.com>
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dt-bindings: iio: adc: Split out QCOM VADC channel properties
prefix all commits with valid tags (FROMLIST etc.)
Add driver for the Qualcomm MBG thermal monitoring device. It monitors the die temperature, and when there is a level 1 upper threshold violation, it receives an interrupt over spmi. The driver reads the fault status register and notifies thermal accordingly. Link: https://lore.kernel.org/all/20260601-spmi-mbg-driver-v1-2-b4892b55a17f@oss.qualcomm.com/ Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Co-developed-by: Sachin Gupta <sachin.gupta@oss.qualcomm.com> Signed-off-by: Sachin Gupta <sachin.gupta@oss.qualcomm.com>
Add macro definitions for virtual channels (combination of ADC channel number and PMIC SID number), to be used in devicetree by clients of ADC5 GEN3 device and in the "reg" property of ADC channels. Link: https://lore.kernel.org/all/20260430-adc5_gen3_dt-v1-1-ab2bb40fd490@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Add ADC nodes for the four PMM8654au PMICs (pmm8654au_0 through pmm8654au_3) on the Lemans platform. Each ADC node exposes the following ADC channels: - DIE_TEMP: PMIC die temperature channel - VPH_PWR: Battery/supply voltage channel Also add the io-channels and io-channel-names properties under the temp-alarm nodes so that they can get temperature reading from the ADC die_temp channels. Link: https://lore.kernel.org/all/20260430-adc5_gen3_dt-v1-2-ab2bb40fd490@oss.qualcomm.com/ Signed-off-by: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Add ADC nodes for PMM8620AU PMIC instances (SID 0 and SID 2) present on the Monaco platform. Each ADC node exposes the following ADC channels: - DIE_TEMP: PMIC die temperature channel - VPH_PWR: Battery/supply voltage channel Link: https://lore.kernel.org/all/20260430-adc5_gen3_dt-v1-3-ab2bb40fd490@oss.qualcomm.com/ Signed-off-by: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Split out the common channel properties for QCOM VADC devices into a separate file so that it can be included as a reference for devices using them. This will be needed for the upcoming ADC5 Gen3 binding support patch, as ADC5 Gen3 also uses all of these common properties. Link: https://lore.kernel.org/all/20260130115421.2197892-2-jishnu.prakash@oss.qualcomm.com/ Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs going through PBS(Programmable Boot Sequence) firmware through a single register interface. This interface is implemented on SDAM (Shared Direct Access Memory) peripherals on the master PMIC PMK8550 rather than a dedicated ADC peripheral. Add documentation for PMIC5 Gen3 ADC and update SPMI PMIC bindings to allow ADC5 Gen3 as adc@ subnode. Link: https://lore.kernel.org/all/20260130115421.2197892-3-jishnu.prakash@oss.qualcomm.com/ Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Acked-by: Lee Jones <lee@kernel.org>
The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2, with all SW communication to ADC going through PMK8550 which communicates with other PMICs through PBS. One major difference is that the register interface used here is that of an SDAM (Shared Direct Access Memory) peripheral present on PMK8550. There may be more than one SDAM used for ADC5 Gen3 and each has eight channels, which may be used for either immediate reads (same functionality as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements (same as ADC_TM functionality). By convention, we reserve the first channel of the first SDAM for all immediate reads and use the remaining channels across all SDAMs for ADC_TM monitoring functionality. Add support for PMIC5 Gen3 ADC driver for immediate read functionality. ADC_TM is implemented as an auxiliary thermal driver under this ADC driver. Link: https://lore.kernel.org/all/20260130115421.2197892-4-jishnu.prakash@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260130115421.2197892-5-jishnu.prakash@oss.qualcomm.com/
…auxiliary driver The SDAM0 IRQ can be triggered for both EOC (end of conversion) events for immediate ADC reads done in this driver and for threshold violation events, based on ADC_TM thresholds configured from the auxiliary ADC_TM driver on TM channels on the first SDAM. At present, this interrupt is handled only in the ISR in the main ADC driver.When the ISR is triggered for an ADC_TM event, this driver notifies the ADC_TM driver by calling a notifier callback exposed from it for this purpose. To simplify the interrupt handling in both drivers, share the interrupt between the drivers. With this, ADC_TM interrupts on SDAM0 will be handled directly in the ADC_TM driver, so remove the notifier callback and all TM interrupt handling in the main ADC ISR. Link: https://lore.kernel.org/all/20260526-gen3_adc_tm-v2-1-702fbac919ac@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Reviewed-by: Jonathan Cameron <jic23@kernel.org>
…oring Add support for ADC_TM part of PMIC5 Gen3. This is an auxiliary driver under the Gen3 ADC driver, which implements the threshold setting and interrupt generating functionalities of QCOM ADC_TM drivers, used to support thermal trip points. Link: https://lore.kernel.org/all/20260526-gen3_adc_tm-v2-2-702fbac919ac@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
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Merge Check Failed: CR Not Eligible for Merge CR 3828090 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
Done. Also I have put every CR in DevComplete still the bot is showing merge failed. |
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Merge Check Failed: CR Not Eligible for Merge CR 3828090 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
Please check the message from bot :
Parent of kernel.qli.2.0 needs to be in dev complete state. |
This series adds support for Qualcomm MBG thermal monitoring and ADc channels.
Adding support for:
DT bindings for the MBG thermal monitor peripheral on PM8775
A new Qualcomm SPMI MBG thermal monitor driver under drivers/thermal/qcom/
The driver monitors die temperature alarms, handles the MBG interrupt on
upper-threshold violation, reads the fault status, and reports events to the
thermal framework.
Link: https://lore.kernel.org/all/20260601-spmi-mbg-driver-v1-0-b4892b55a17f@oss.qualcomm.com/
Link: https://lore.kernel.org/all/20260430-adc5_gen3_dt-v1-0-ab2bb40fd490@oss.qualcomm.com/
Link: https://lore.kernel.org/all/20260526-gen3_adc_tm-v2-0-702fbac919ac@oss.qualcomm.com/
Link: https://lore.kernel.org/all/20260130115421.2197892-1-jishnu.prakash@oss.qualcomm.com/
CRs-Fixed: 3828090, 3871464, 3947936, 3974949
RFC patch: https://lore.kernel.org/all/qq3cggafexwpdrv46eqijxfmrdbqusl2vpbuswqmcvshqueaiw@r4mrmap4nwkt/
qli-2.0 GA Critical Fix